The single crystal of silicon carbide (SiC) has excellent physical properties, such as a wide band gap, a high dielectric breakdown intensity and a large saturation drift velocity of electrons, as compared with the single crystal of silicon (Si). Therefore, use of SiC as the constitutive material makes it possible to fabricate a semiconductor device for use with an electrical power of high withstand voltage and low resistance exceeding Si. In addition, like Si, SiC is characterized in that it may form an insulating layer through thermal oxidation. These facts lead to a supposition that the fabrication of a vertical MOSFET having a high withstand voltage and a low on-resistance and using the single crystal of SiC as the constitutive material is feasible. Numerous researches and developments directed to this fabrication have been under path.
When SiC is used as the constitutive material, a vertical MOSFET (D-MOSFET) could not be fabricated by the double diffusion method that is generally applied to Si. This is because the diffusion coefficient of impurity dopants is extremely small in the crystal of SiC and the formation of channel regions is consequently precluded by the difference in the transverse diffusion length between the p-type and n-type impurity dopants. Thus, the vertical MOSFET similar to D-MOSFET of Si is fabricated through ion implantation of p-type and n-type impurities (double ion implantation method). This method, however, degrades the electron mobility because numerous crystal defects induced by ion implantation remain in the channel region and scatter the conductive electrons induced in the channel. The SiC vertical MOSFET fabricated according to the double ion implantation method has a channel mobility of from 5 to 10 cm2/Vs, an extremely small value as compared with the channel mobility of about 500 cm2/Vs that the Si D-MOSFET has. As a result, the device entails a problem in that its on-resistance is far higher than the theoretical value thereof.
As a means to solve this problem, a configuration that forms the channel region not by ion implantation but with a deposition film has been proposed. A typical examples of this configuration is disclosed in Patent Reference 1 that was filed on Oct. 3, 2003. FIG. 7 is a cross-sectional view of the unit cell of the configuration. In this configuration, a low-concentration n-type drift layer 2 is deposited on a high-concentration n-type substrate 1, a high-concentration p-type gate layer 31 is formed by ion implantation on the surface of the n-type drift layer 2, and a low-concentration p-type layer 32 is deposited further thereon. On the surface part of the low-concentration p-type layer 32, an n-type source layers 51 and 52 are selectively formed by ion implantation, a gate electrode 7 is formed via a gate oxide film 6, and further a source electrode 9 is formed via an interlayer insulation film 8. Channel regions 11 and 12 are formed in the low-concentration p-type deposition layer 32 directly below the gate oxide film 6. The configuration is characterized in that an electron guide path 40 penetrating through the low-concentration p-type deposition layer 32 and reaching the n-type drift layer 2 is selectively formed through ion implantation of an n-type impurity from the surface (hereinafter the electron guide path 40 will be occasionally referred to as a “inverted layer 40”). Since this configuration has the channel regions 11 and 12 formed in the low-concentration p-type deposition layer that has undergone no ion implantation, it is capable of acquiring a high mobility of conductive electrons and permitting fabrication of a vertical MOSFET having a small on-resistance. It is further characterized in that the leak of an electric field into the gate oxide film near the channel regions 11 and 12 can be prevented and the source/drain withstand voltage can be heightened because the depletion layer transversely extending from the high-concentration p-type gate layer 31 to the low-concentration n-type drift layer 2 in the state of voltage block enables the vertical channel part 24 to be completely pinched off at a low voltage.
However, this configuration entails a problem that makes it difficult to satisfy both high withstand voltage and low on-resistance, as described below. This is based on the difference between the length a and the length b of the channel regions 11 and 12 formed on the right and left sides of the inverted layer 40. Before the reason is described in detail, first described hereinunder is the reason why there occurs the difference between the length a and the length b in the conventional configuration and according to its production method.
FIG. 8(a) to (e) show a part of a process for producing the SiC-MOSFET having a conventional configuration shown in FIG. 7. These are cross-sectional views of the unit cell of the configuration. First, a low-concentration n-type drift layer 2 doped with 5×1015 cm−3 of nitrogen is deposited on a high-concentration n-type substrate 1 to a thickness of 15 μm (a). Next, a high-concentration p-type layer 31 is formed through p-type impurity ion implantation 3a via a mask 130 (b). The mask 130 is formed by patterning through photolithography of an SiO2 film deposited on the surface according to a reduced-pressure CVD method. After the mask is removed, a low-concentration p-type layer 32 doped with 5×1015 cm−3 of aluminum is deposited on the surface to a thickness of about 0.5 μm (c). Next, an n-type inverted layer 40 is formed through n-type impurity ion implantation 4a via a mask 140, and the implanted region is converted (reversed) from p-type to n-type (d). For the n-type impurity ion implantation 4a, nitrogen ions are implanted at room temperature at an acceleration energy of from 40 keV to 250 keV to a dose of 1×1016 cm−3. After the mask 140 is removed, n-type source layers 51 and 52 are formed through n-type impurity ion implantation 5a via a mask 150 (e). For the n-type impurity ion implantation 5a, phosphorus ions are implanted at a substrate temperature of 500° C. at an acceleration energy of from 40 keV to 250 keV to a dose of 2×1020 cm−3. Next, this is annealed for activation in an argon atmosphere at 1500° C. for 30 minutes, and a gate insulation film 6, a gate electrode 7, a source electrode 9 and a drain electrode 10 are formed to complete the device.
In the production process, the inverted layer 40 and the n-type source layers 51 and 52 are formed according to an ion implantation method using different implantation masks 140 and 150. Accordingly, the distance to the position at which the n-type source layers 51 and 52 are formed, relative to the position at which the inverted layer 40 is formed, is not always the same. Specifically, this depends on the positioning accuracy in photolithography in mask-patterning the layers, and even under the most careful positioning operation, there may occur a position shift within a positioning accuracy of the alignment device itself of generally about 0.5 μm. As a result, there may be a dimensional difference of 2 times the position shift between the length a and the length b of the channel regions 11 and 12 to be defined as a relative position to the right and left edges of the inverted layer 40 and the right side edge of the n-type source layer 51 and the left side edge of 52. In general, the length of the channel regions 11 and 12 (the value of a, b) is planned to be from 1.0 to 1.5 μm or so, and in case where the length is taken as 1.0 μm and the position shift of the two masks is the same, 0.5 μm, as that of the positioning accuracy of the alignment device, then the length a is 1.5 μm but the length b is 0.5 μm, of that is, there occurs a difference of 1.0 μm between the lengths a and b.
The above description relates to the difference between the length of the right-side channel region and that of the left-side channel region in one unit cell; but in a practical device, a large number of cells, or that is, more than tens of thousands of cells are aligned in parallel in a semiconductor chip having a few mm square, and between the cells in the chip, there may occur a difference in the length between the channel regions. Accordingly, in one device, the ununiformity of the length of the channel regions further expands.
The conventional configuration in which the length of the channel region differs not only in a unit cell but also between unit cells constituting a device in the manner as above has an extremely serious problem in that it could not satisfy the requirement of low on-resistance and high withstand voltage of MOSFET. This is described below. Specifically, this configuration is characterized in that the leak of an electric field into the gate oxide film near the channel regions 11 and 12 can be prevented and the source/drain withstand voltage can be heightened because the depletion layer transversely extending from the high-concentration p-type gate layer 31 to the low-concentration n-type drift layer 2 in the state of voltage block enables the vertical channel part 24 to be completely pinched off at a low voltage. In this state, the voltage of from 30 to 50 V before the complete pinching off of the vertical channel part 24 must be blocked in the horizontal MOSFET part that comprises the n-type inverted layer 40, the p-type channel regions 11 and 12, the n+ source layers 51 and 52, the gate oxide film 6 and the gate 7. When the horizontal MOSFET part could not block the voltage of from 30 to 50 V, then source/drain withstand of the vertical MOSFET of this configuration is greatly degraded. The voltage block characteristic of this part is defined by the punch-through voltage in the npn transistor part composed of n-type inverted layer/p-type channel region/n+ source layer. In other words, this greatly depends on the impurity concentration and the length (value a, b) of the p-type channel regions 11 and 12, and for keeping a punch-through voltage of from 30 to 50 V or more, these must be larger than predetermined values. However, for reducing the on-resistance of the vertical MOSFET, the channel mobility thereof must be increased, and therefore, the p-type impurity concentration in the channel regions 11 and 12 are reduced as much as possible and at the same time the length of the channel regions is shortened as much as possible to thereby reduce the channel resistance as much as possible. Accordingly, the degree of freedom in planning the impurity concentration and the length (that is, the length a and the length b) of the channel regions 11 and 12 is small, and in general, the p-type impurity concentration is planned to be from 5×1015 to 1×1016 cm−3 and the length is to be from 1.0 to 1.5 μm or so, as so mentioned in the above. In the thus-planned MOSFET, when any of the length a or b is made smaller than the defined value owing to the limitation to the positioning accuracy in the production process as described in [0007], then the withstand voltage of the vertical MOSFET greatly lowers.
FIG. 9 shows experimental examples of the relation between the channel length LG and the drain/source withstand voltage VBD of a vertical MOSFET having a conventional configuration. The data of three test lots (black circle, black square, black triangle) are shown. In this, the channel length LG is not a found value, but is a planned length in a virtual case where the mask positioning accuracy is estimated as ±0 μm. When the channel length is 1.5 μm, all the three cases have a withstand voltage of 800 V; but when the channel length is 1.2 μm, then the withstand voltage is from 600 V to 700 V, and further when the channel length is 1.0 μm, then the withstand voltage is from tens V to 400 V. Thus, the withstand voltage fluctuates greatly. The reason for the extreme reduction and fluctuation in the withstand voltage may be considered because, as so mentioned in the above, the channel length LG fluctuated within a range of from 0.5 μm to 1.5 μm owing to the mask positioning failure in the actual device, and at the site having a smallest LG, the device showed a low withstand voltage.
As in these experimental examples, when the channel length is designed to be at least 1.5 μm, then devices having a predetermined withstand voltage can be produced at a high yield, but on the other hand, the devices shall have a large on-resistance in proportion to the channel length thereof. In addition, for devices having a further higher withstand voltage, the channel length must be set further longer, therefore bringing about a problem in that the on-resistance of the devices increases further. Specifically, vertical MOSFET devices having a conventional configuration and produced according to a conventional method could hardly satisfy both the requirement of low on-resistance and the requirement of high withstand voltage.
To solve the problem that, owing to the limitation to the positioning accuracy in the production process, a part having a short channel length may form as in the above and the withstand voltage is thereby lowered, a modification may be taken into consideration for the conventional production process shown in FIG. 8. Concretely, in the step (d) to form the inverted layer 40 through nitrogen ion implantation, the implantation mask 140 is holed to have an opening at nearly the same position as the position at which the source layers 51 and 52 are formed, and also in the opening, nitrogen ion are implanted to thereby form the inverted layer 40 and the source layers 51 and 52 all at the same time. In this case, however, there is a problem in that, since the nitrogen dope concentration in the source layer part could not fully increase, the resistance inside the source layer and the contact resistance of the source contact increase. When high-concentration phosphorus ions are implanted in the step (e), using the same mask, then the problem of the source layer concentration could be solved, but the impurity concentration in the inverted layer part increases too much, therefore often causing a problem of dielectric breakdown since a strong electric field is applied to the gate oxide film 6 existing between the gate electrode 7 and the inverted layer before the vertical channel part is completely pinched off. In addition, after the vertical channel part has been pinched off, the electric field may be further strengthened owing to the voltage increase, and owing to the dielectric breakdown of the gate oxide film in this part, there occurs still another problem in that the source/drain withstand voltage shall be limited to be low. Anyhow, the conventional configuration and the conventional production method have extremely serious problems in that MOSFET could hardly satisfy both the requirement of low on-resistance and the requirement of high withstand voltage. Patent Reference 1: WO04/036655